1. Field of Invention
The present invention relates to a packaging structure for a silicon chip. More particularly, the present invention relates to a ball grid array package with conductive leads.
2. Description of Related Art
In the manufacturing of integrated circuits, ultimate size of the package is an important issue. As the level of integration and functions of integrated circuits increase, the number of conductive leads required for connections with external circuitry are also increased. Furthermore, as the operating speed of silicon chip continue to increase, the amount of heat generated by the chip and electrical interference caused by external electromagnetic fields during operation can no longer be ignored. An increase in the level of integration leads to an increase in conductive lead-count under the same chip volume. However, when the number of conductive leads increases, distance between neighboring leads have to become smaller, thereby increasing the level of difficulties in packaging a silicon chip. Consequently, a packaging structure has been developed from the peripheral-arranged leadframe structure to a high-density area array structure. A typical high-density area array structure is the ball grid array (BGA) structure. To further reduce the footprint requirement of a ball grid array assembly and increase the number of conductive leads available, a ball grid array structure having additional conductive leads around the periphery of the package has been developed as well. Nonetheless, the thermal efficiency and the electromagnetic interference problems need to be carefully considered in the design of a high-density area array package.
FIG. 1 is a schematic, cross-sectional view showing a typical ball grid array package having a heat sink and conductive leads. As shown in FIG. 1, a silicon chip 10 is mounted on a surface of substrate 12. A heat sink 16 is directly mounted on top of the silicon chip 10 so that heat generated by the chip 10 during operation can be conducted away rapidly. The conductive leads 14 are mounted on the substrate 12 and surrounding the chip 10. A back surface of the chip 10 is thermally coupled to some solder balls 19' on another surface of the substrate 12 so that heat can also be conducted away, In general, the substrate 12 is laminated with each layer includes some conductive traces. Different trace layers are electrically connected by vias. Furthermore, the trace layer located on the surface of the substrate 12 possesses contact points 13 for electrical connections with the silicon chip 10. A plurality of solder balls 19 is placed on the other side of the substrate 12 for electrical connections with a printed circuit board. The silicon chip 10 is electrically connected to the contact points 13 and the conductive leads 14 through electrical wires 15 and 17, respectively. Hence, electrical signals within the chip 10 are able to pass onto the substrate 12 and the conductive leads 14. A molding compound 18 encloses the silicon chip 10 and the wires 15 and 17. The molding compound 18 also fills the space between the heat sink 16, the chip 10, the conductive leads 14, and the substrate 12 while exposing a surface of the heat sink 16. Thus, the chip 10, the substrate 12, and inner portion of the leads 14 are protected while heat can be conducted away through the exposed surface of the heat sink 16.
The aforementioned package structure not only has an area array of solder balls, but also contains a plurality of conductive leads 14 coming out from the edge of the package. Hence, the package can have a relatively small footprint while the number of connections is maintained. However, the heat sink 16 is a structure that floats above the silicon chip 10, and electric charges may accumulate. Thereby, a parasitic capacitance may be generated leading to the distortion of signals from the chip 10.